1. Field of the Invention
The present invention generally relates to insulated gate MOS transistors. More specifically, the present invention relates to the protectionxe2x80x94or hardeningxe2x80x94of such MOS transistors against ionizing particles.
2. Discussion of the Related Art
Under the effect of ionizing particles, such as for example, heavy ions, protons, alpha particles, it can be observed that MOS transistors, controlled to be off, turn on. This is more particularly observed upon impact of such particles in drain areas, identified as being the most sensitive. This results in untimely switchings that disturb or even damage the devices incorporating these transistors. For example, in SRAM devices, such disturbances are capable of causing the change of the stored logic state to change.
The reduction of transistor dimensions increases the sensitivity of transistors to such impacts.
To overcome the effects of such disturbances, different techniques have been provided. Various non-limiting solutions provided in the specific case of SRAM-type memories will be discussed hereafter.
A first approach consists of providing around the device a shielding, for example made of aluminum, absorbing the particle energy. Such a shielding is bulky and expensive, all the more as it must be thick to be able to absorb the more energetic particles.
A second approach consists of modifying the circuit to enable a cell to return to its initial state after a disturbance. Such modifications consist, for example, of providing additional cells (redundancy), or of modifying the very structure of the elementary six-transistor SRAM cells to guarantee the locking of the stored data. Cells with at least ten transistors or with a resistive decoupling have thus been provided. However, such modifications considerably reduce the cell performance, for example in terms of increasing access time and/or increasing power consumption. Further, they complicate the monolithic implementation of memory devices and/or increase their bulk, which results in a reduced memory density.
A third approach consists of modifying the MOS transistor manufacturing technology. Silicon-on-insulator (SOI) technologies have thus been used. Although the observed performance reductions (increased access time, increased power consumption, increased bulk) are then smaller than with the other techniques already provided, such technologies are particularly complex and expensive to implement.
It has also been provided to make insensitivexe2x80x94to xe2x80x9chardenxe2x80x9dxe2x80x94the very individual transistors. However, this is performed by oversizing the transistor (increase of the channel area). Such a solution is incompatible with the goal of reducing transistor dimensions. A SRAM formed from such transistors would be slow and have a small density.
An object of the present invention is to provide a novel structure of MOS transistors with a robust hardening against ionizing particles.
Another object of the present invention is to provide such a structure which induces manufacturing constraints (complexity, cost) that are negligible, or at least much smaller than those induced by present solutions.
Another object of the present invention is to provide a hardened SRAM-type memory cell structure using the transistors according to the present invention.
Another object of the present invention is to provide such a hardened memory structure that has a limited bulk as compared to existing solutions.
Another object of the present invention is to provide such a memory structure that has performances comparable to those of a conventional memory.
To achieve these and other objects, the present invention provides a lateral MOS transistor including a gate and drain and source regions of a first conductivity type formed in a substrate of a second conductivity type connected to a first power supply, wherein a doped buried layer of the first conductivity type extends under said drain region and under a portion of the gate, the buried layer being connected to the gate via a one-way conduction connection.
According to an embodiment of the present invention, the one-way conduction means is a diode, the cathode of which is connected to the transistor gate and the anode of which is connected to the buried layer.
According to an embodiment of the present invention, the connection of the substrate to the first power supply is ensured by a heavily-doped deep region of the second conductivity type extending to reach a more heavily-doped portion of said substrate.
The present invention also provides a SRAM-type memory cell, two first N-channel transistors of the cell having structures according to the preceding embodiment, and two second P-channel transistors of the cell being formed in an N-type well next to the area in which are formed the first transistors, the drain regions of the second transistors being formed close to said heavily-doped region of the first transistors.
The foregoing objects, features and advantages of the present invention, will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.